The present invention disclosed herein relates to an error amplifier, and more particularly, to an error amplifier having a cascode current source using body biasing.
Recently, mobility increase due to the rapid development of information and communication technology and the development of transportation brings the drastic increases of portable electronic product markets. Simultaneously, a miniaturization trend on a charger or adapter of an electronic product comes to the fore. That is, according to the development of an integrated circuit technology and the cultural needs of the consumers, production and sale of portable multimedia devices having various functions, small area, and light weight are increased.
Accordingly, a battery based portable electronic device such as a smart phone, a navigation system, and an MP3 player is manufactured focusing on size, speed, and power management. Especially, in order to implement a small area, an integrated circuit technology for integrating various chips, used for driving portable devices, into one chip is being developed. That is, in order to realize various functions in the same chip area, an integrated circuit technology having typical circuit characteristics but a reduced area is being developed.
As one of blocks for designing a power management integrated circuit (PMIC), an error amplifier is being designed and developed. An error amplifier detects and amplifies errors of an output voltage and a feedback voltage, and maintains a feedback system to secure circuit stability. Moreover, the error amplifier may change the number of stages for gain according to a usage purpose or may install a compensation stage to obtain the stability of a feedback system, with various structures.
Moreover, the error amplifier may increase the size of a transistor during a design process or makes it in symmetry during a design process in order to obtain the same result as a simulation. Accordingly, the error amplifier may reduce errors occurring during manufacturing processes. Especially, a technology for designing a large area to reduce errors occurring during processes may affect various factors such as parasite component increase, speed, and stability due to the size increase of a transistor. Furthermore, as interest is on the miniaturization of an electronic device, a technology for reducing the size of an IC-chip and providing the same or high performance becomes required. Accordingly, a technology of a circuit design for providing the same performance and a small area is being developed.